1. A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

  2. Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes

  3. Area-Delay Efficient Binary Adders in QCA

  4. Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip 

  5. Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure

  6. VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor

  7. A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing

  8. Effective and efficient approach for power reduction by using multi-bit flip-flops

  9. FPGA Implementation of FFT Algorithm for IEEE 802.16e (Mobile wimax)

  10. Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System

  11. Design of Testable Reversible Sequential Circuits

  12. Glitch-Free NAND-Based Digitally Controlled delay lines

  13. The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures

  14. Constant Delay Logic Style

  15. Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

  16. Design of Ternary Logic Combinational circuits Based on Quantum Dot Gate FETs

  17. A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

  18. Self-Repairing Digital System with Unified Recovery Process Inspired by Endocrine Cellular Communication

  19. Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes

  20. Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications

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