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VLSI 2015 TITLES

2015

  1. A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register

  2. A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply

  3. A Low-Power Robust Easily CascadedPentaMTJ-Based Combinational and Sequential Circuits

  4. A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

  5. A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-Mw Current-Steering DAC in 0.038 mm2

  6. Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

  7. Design and Low-Complexity Implementation of Matrix–Vector Multiplier for Iterative Methods in Communication Systems

  8. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology

  9. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks

  10. Graph-Based Transistor Network Generation Method for Supergate Design

  11. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

  12. High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

  13. A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices

  14. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

  15. Further Desensitized FIR Halfband Filters

  16. A Modified Partial Product Generator for Redundant Binary Multipliers

  17. Implementation of Arithmetic Operations with Time-free Spiking Neural P Systems

  18. A Clock and Data Recovery Circuit With Programmable Multi-Level Phase Detector Characteristics and a Built-in Jitter Monitor

  19. Unfaithful Glitch Propagation in Existing Binary Circuit Models

  20. Early Skip Mode Decision for HEVC Encoder With Emphasis on Coding Quality

  21. Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters

  22. Energy Consumption of VLSI Decoders

  23. Timing Error Tolerance in Small Core Designs for SoC Applications

  24. 40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

  25. Design and Analysis of Inexact Floating-Point Adders

  26. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

  27. Low-Cost High-Performance VLSI Architecture for Montgomery ModularMultiplication

  28. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

  29. Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA

  30. A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory

  31. Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception

  32. Synthesis of Genetic Clock with Combinational Biologic Circuits

  33. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

  34. Fault Tolerant Parallel Filters Based on Error Correction Codes

  35. Design and Analysis of Approximate Compressors for Multiplication

  36. Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number Systems

  37. An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability

  38. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

  39. Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application

  40. Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications

  41. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

  42. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

  43. Low-Power and Area-Efficient Shift Register Using Pulsed Latches

  44. Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design

  45. Recursive Approach to the Design of a Parallel Self-Timed Adder

  46. Further Desensitized FIR Half band Filters

  47. Design and Analysis of Inexact Floating-Point Adder

  48. Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq

  49. An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis

  50. A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT


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