VLSI OLD IEEE TITLES

OLD IEEE

  1. High Resolution Application Specific Fault Diagnosis Of FPGAs

  2. Design of HDLC Controller Using VHDL

  3. Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

  4. Truncation-Error-Tolerant Adder and Its 

  5. Application in Digital Signal Processing

  6. A High-Speed, Energy-Efficient Two-Cycle

  7. Multiply-Accumulate (MAC) Architecture and Its

  8. Application to a Double-Throughput MAC Unit

  9. Hazard-Based Detection Conditions for Improved

  10. Transition Fault Coverage of Scan-Based Tests

  11. LUT Optimization for Memory-Based Computation

  12. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

  13. Multiplier–Accumulator Based on Radix-2

  14. A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

  15. New Reconfigurable Architectures for Implementing FIR Filters with Low Complexity

  16. Partial-Matching Technique in a Mixed-Mode BIST Environment

  17. A Low-Power FPGA Based on Autonomous

  18. Fine-Grain Power Gating

  19. Recursive Pseudo-Exhaustive Two-Pattern Generation

  20. Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects

  21. Self-Test Techniques for Crypto-Devices

  22. Design and Analysis of High-Throughput Lossless Image Compression Engine Using VLSI-Oriented FELICS Algorithm

  23. Voltage Scalable High-Speed Robust Hybrid

  24. Arithmetic Units Using Adaptive Clocking

  25. Test Data Compression Using Efficient Bitmask andDictionary Selection Methods

  26. High Volume Diagnosis in Memory BIST Based on Compressed Failure Data

  27. FPGA Design for Multi-Filtering Techniques Using Flag-Bit and Flicker Clock

  28. Hardware-Efficient Prediction-Correction-Based Generalized

  29. Voronoi-Diagram Construction and FPGA Implementation

  30. A Novel Control System Processor and Its VLSI Implementation

  31. Exploiting Parallelism in Double Path Adders' Structure

  32. for Increased Throughput of Floationg Point Addition

  33. Design of an Interconnect Architecture and Signaling

  34. Technology for Parallelism in Communication


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