VLSI PROJECT ABSTRACTS

  1. A Low-Power Single-Phase Clock Multiband Flexible Divider

  2. A Novel Modulo Adder for 2N-2K-1 Residue Number System

  3. Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

  4. An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

  5. Area-Delay Efficient Binary Adders in QCA

  6. Area–Delay–Power Efficient Carry-Select Adder

  7. Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay

  8. Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation

  9. Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm

  10. Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

  11. Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter

  12. Efficient Integer DCT Architectures for HEVC

  13. Eliminating Synchronization Latency Using Sequenced Latching

  14. Fast Sign Detection Algorithm for the RNS Moduli Set 2n+1-1, 2n-1, 2n

  15. Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits

  16. High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic

  17. Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

  18. Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

  19. Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

  20. Multifunction Residue Architectures for Cryptography

  21. Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks with Low Adder-Count

  22. Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations

  23. Incremental Trace-Buffer Insertion for FPGA Debug

  24. LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

  25. Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits

  26. A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals

  27. Pulsed-Latch Utilization for Clock-Tree Power Optimization

  28. On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

  29. Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method

  30. Ultra-High Throughput Low-Power Packet Classification

  31. Variation-Aware Variable Latency Design

  32. High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

  33. On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions

  34. Delay Test for Diagnosis of Power Switches

  35. Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

  36. Pulsed-Latch Utilization for Clock-Tree Power Optimization


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